Designing Asynchronous Circuits using NULL Convention Logic (NCL) - read free eBook in online reader or directly download on the web page. Select files or add your book in reader. Download and read online ebook Designing Asynchronous Circuits using NULL Convention Logic (NCL) write by Scott Smith. This book was released on 2022-06-01. Designing Asynchronous Circuits using NULL Convention Logic (NCL) available in PDF, EPUB and Kindle. Designing Asynchronous Circuits using NULL Convention Logic (NCL) begins with an introduction to asynchronous (clockless) logic in general, and then focuses on delay-insensitive asynchronous logic design using the NCL paradigm. The book details design of input-complete and observable dual-rail and quad-rail combinational circuits, and then discusses implementation of sequential circuits, which require datapath feedback. Next, throughput optimization techniques are presented, including pipelining, embedding registration, early completion, and NULL cycle reduction. Subsequently, low-power design techniques, such as wavefront steering and Multi-Threshold CMOS (MTCMOS) for NCL, are discussed. The book culminates with a comprehensive design example of an optimized Greatest Common Divisor circuit. Readers should have prior knowledge of basic logic design concepts, such as Boolean algebra and Karnaugh maps. After studying this book, readers should have a good understanding of the differences between asynchronous and synchronous circuits, and should be able to design arbitrary NCL circuits, optimized for area, throughput, and power. Table of Contents: Introduction to Asynchronous Logic / Overview of NULL Convention Logic (NCL) / Combinational NCL Circuit Design / Sequential NCL Circuit Design / NCL Throughput Optimization / Low-Power NCL Design / Comprehensive NCL Design Example
Design and Implementation of an Asynchronous NULL Convention Logic (NCL) FPGA
Design and Implementation of an Asynchronous NULL Convention Logic (NCL) FPGA - read free eBook in online reader or directly download on the web page. Select files or add your book in reader. Download and read online ebook Design and Implementation of an Asynchronous NULL Convention Logic (NCL) FPGA write by Indira Priyadarshini Dugganapally. This book was released on 2009. Design and Implementation of an Asynchronous NULL Convention Logic (NCL) FPGA available in PDF, EPUB and Kindle. "This Master's thesis outlines the design of a completely asynchronous Field Programmable Gate Array (FPGA) for implementing NULL Convention Logic (NCL) digital circuits. The proposed design uses four Configurable Logic Blocks (CLB), each of which in turn is designed using four Logic Elements (LE) to implement NCL logic function. Each LE can be configured to function as any one of the 27 fundamental NCL gates. A Logic Element is designed by concatenating a Look-Up-Table (LUT) with a pull-up pull-down transistor chain and a hysteresis loop. The interconnections and the switch box are designed using pass transistors and SRAM. In this thesis, a 4-input Look-Up Table (LUT) based 16-gate FPGA specifically for NCL circuits was designed and successfully programmed as a dual-rail non-pipelined 4-bit NCL register. The design was first created using the schematic capture, followed by layout or the physical level designs subsequent to successful simulation. The NCL FPGA is simulated at the transistor level using the 1.8V, 180nm TSMC CMOS process. The size of FPGAs is now more than 1 million equivalent gates, making them a viable alternative to custom design for all but the most complex processors. FPGAs are relatively low-cost and are reconfigurable, making them perfect for prototyping, as well as implementing the final design, especially for low volume production. To compete with this cheap, reconfigurable synchronous implementation, an NCL-specific FPGA is needed, such that NCL circuits can be implemented without necessitating a prohibitively expensive full-custom design"--Abstract, leaf iii.
An Asynchronous FPGA for NULL Convention Logic Circuits
An Asynchronous FPGA for NULL Convention Logic Circuits - read free eBook in online reader or directly download on the web page. Select files or add your book in reader. Download and read online ebook An Asynchronous FPGA for NULL Convention Logic Circuits write by Arun Swaminathan Balasubramanian. This book was released on 2005. An Asynchronous FPGA for NULL Convention Logic Circuits available in PDF, EPUB and Kindle. "This Master's thesis is intended to familiarize the reader with the asynchronous delay-insensitive NULL convention Logic (NCL) paradigm and illustrate the design of a completely asynchronous Field Programmable Gate Array (FPGA) for NULL Convention Logic circuits. Mentor Graphics Design Automation tools such as Design Architect and Accusim II were extensively used in creating this design"--Introduction, leaf 1.
Designing Asynchronous Circuits Using NULL Convention Logic (NCL)
Designing Asynchronous Circuits Using NULL Convention Logic (NCL) - read free eBook in online reader or directly download on the web page. Select files or add your book in reader. Download and read online ebook Designing Asynchronous Circuits Using NULL Convention Logic (NCL) write by Scott C. Smith. This book was released on 2009. Designing Asynchronous Circuits Using NULL Convention Logic (NCL) available in PDF, EPUB and Kindle. Designing Asynchronous Circuits using NULL Convention Logic (NCL) begins with an introduction to asynchronous (clockless) logic in general, and then focuses on delay-insensitive asynchronous logic design using the NCL paradigm. The book details design of input-complete and observable dual-rail and quad-rail combinational circuits, and then discusses implementation of sequential circuits, which require datapath feedback. Next, throughput optimization techniques are presented, including pipelining, embedding registration, early completion, and NULL cycle reduction. Subsequently, low-power design techniques, such as wavefront steering and Multi-Threshold CMOS (MTCMOS) for NCL, are discussed. The book culminates with a comprehensive design example of an optimized Greatest Common Divisor circuit. Readers should have prior knowledge of basic logic design concepts, such as Boolean algebra and Karnaugh maps. After studying this book, readers should have a good understanding of the differences between asynchronous and synchronous circuits, and should be able to design arbitrary NCL circuits, optimized for area, throughput, and power. Table of Contents: Introduction to Asynchronous Logic / Overview of NULL Convention Logic (NCL) / Combinational NCL Circuit Design / Sequential NCL Circuit Design / NCL Throughput Optimization / Low-Power NCL Design / Comprehensive NCL Design Example
Technology Mapping, Design for Testability, and Circuit Optimizations for NULL Convention Logic Based Architectures
Technology Mapping, Design for Testability, and Circuit Optimizations for NULL Convention Logic Based Architectures - read free eBook in online reader or directly download on the web page. Select files or add your book in reader. Download and read online ebook Technology Mapping, Design for Testability, and Circuit Optimizations for NULL Convention Logic Based Architectures write by Farhad Alibeygi Parsan. This book was released on 2014. Technology Mapping, Design for Testability, and Circuit Optimizations for NULL Convention Logic Based Architectures available in PDF, EPUB and Kindle. Delay-insensitive asynchronous circuits have been the target of a renewed research effort because of the advantages they offer over traditional synchronous circuits. Minimal timing analysis, inherent robustness against power-supply, temperature, and process variations, reduced energy consumption, less noise and EMI emission, and easy design reuse are some of the benefits of these circuits. NULL Convention Logic (NCL) is one of the mainstream asynchronous logic design paradigms that has been shown to be a promising method for designing delay-insensitive asynchronous circuits. This dissertation investigates new areas in NCL design and test and is made of three sections. The first section discusses different CMOS implementations of NCL gates and proposes new circuit techniques to enhance their operation. The second section focuses on mapping multi-rail logic expressions to a standard NCL gate library, which is a form of technology mapping for a category of NCL design automation flows. Finally, the last section proposes design for testability techniques for a recently developed low-power variant of NCL called Sleep Convention Logic (SCL).
