Energy-Efficient VLSI Architectures for Real-Time and 3D Video Processing - read free eBook in online reader or directly download on the web page. Select files or add your book in reader. Download and read online ebook Energy-Efficient VLSI Architectures for Real-Time and 3D Video Processing write by Michael Stefano Fritz Schaffner. This book was released on 2017. Energy-Efficient VLSI Architectures for Real-Time and 3D Video Processing available in PDF, EPUB and Kindle.
Energy-Efficient VLSI Architectures for Real-Time and 3D Video Processing
Energy-Efficient VLSI Architectures for Real-Time and 3D Video Processing - read free eBook in online reader or directly download on the web page. Select files or add your book in reader. Download and read online ebook Energy-Efficient VLSI Architectures for Real-Time and 3D Video Processing write by Michael Stefano Fritz Schaffner. This book was released on 2018-10-24. Energy-Efficient VLSI Architectures for Real-Time and 3D Video Processing available in PDF, EPUB and Kindle. Multiview autostereoscopic displays (MADs) make it possible to view video content in 3D without wearing special glasses, and such displays have recently become available. The main problem of MADs is that they require several (typically 8 or 9) views, while most of the 3D video content is in stereoscopic 3D today. To bridge this content-display gap, the research community started to devise automatic multiview synthesis (MVS) methods. Common MVS methods are based on depth-image-based rendering, where a dense depth map of the scene is used to reproject the image to new viewpoints. Although physically correct, this approach requires accurate depth maps and additional inpainting steps. Our work uses an alternative conversion concept based on image domain warping (IDW) which has been successfully applied to related problems such as aspect ratio retargeting for streaming video, and dispa- rity remapping for depth adjustments in stereoscopic 3D content. IDW shows promising performance in this context as it only requires robust, sparse point- correspondences and no inpainting steps. However, MVS, using IDW as well as alternative approaches, is computationally demanding and requires realtime processing - yet such methods should be portable to end-user and even mobile devices to develop their full potential. To this end, this thesis investigates efficient algorithms and hardware architectures for a variety of subproblems arising in the MVS pipeline.
An Event-Driven Parallel-Processing Subsystem for Energy-Efficient Mobile Medical Instrumentation
An Event-Driven Parallel-Processing Subsystem for Energy-Efficient Mobile Medical Instrumentation - read free eBook in online reader or directly download on the web page. Select files or add your book in reader. Download and read online ebook An Event-Driven Parallel-Processing Subsystem for Energy-Efficient Mobile Medical Instrumentation write by Florian Stefan Glaser. This book was released on 2022-12-02. An Event-Driven Parallel-Processing Subsystem for Energy-Efficient Mobile Medical Instrumentation available in PDF, EPUB and Kindle. Aging population and the thereby ever-rising cost of health services call for novel and innovative solutions for providing medical care and services. So far, medical care is primarily provided in the form of time-consuming in-person appointments with trained personnel and expensive, stationary instrumentation equipment. As for many current and past challenges, the advances in microelectronics are a crucial enabler and offer a plethora of opportunities. With key building blocks such as sensing, processing, and communication systems and circuits getting smaller, cheaper, and more energy-efficient, personal and wearable or even implantable point-of-care devices with medicalgrade instrumentation capabilities become feasible. Device size and battery lifetime are paramount for the realization of such devices. Besides integrating the required functionality into as few individual microelectronic components as possible, the energy efficiency of such is crucial to reduce battery size, usually being the dominant contributor to overall device size. In this thesis, we present two major contributions to achieve the discussed goals in the context of miniaturized medical instrumentation: First, we present a synchronization solution for embedded, parallel near-threshold computing (NTC), a promising concept for enabling the required processing capabilities with an energy efficiency that is suitable for highly mobile devices with very limited battery capacity. Our proposed solution aims at increasing energy efficiency and performance for parallel NTC clusters by maximizing the effective utilization of the available cores under parallel workloads. We describe a hardware unit that enables fine-grain parallelization by greatly optimizing and accelerating core-to-core synchronization and communication and analyze the impact of those mechanisms on the overall performance and energy efficiency of an eight-core cluster. With a range of digital signal processing (DSP) applications typical for the targeted systems, the proposed hardware unit improves performance by up to 92% and 23% on average and energy efficiency by up to 98% and 39% on average. In the second part, we present a MCU processing and control subsystem (MPCS) for the integration into VivoSoC, a highly versatile single-chip solution for mobile medical instrumentation. In addition to the MPCS, it includes a multitude of analog front-ends (AFEs) and a multi-channel power management IC (PMIC) for voltage conversion. ...
Fighting Back the Von Neumann Bottleneck with Small- and Large-Scale Vector Microprocessors
Fighting Back the Von Neumann Bottleneck with Small- and Large-Scale Vector Microprocessors - read free eBook in online reader or directly download on the web page. Select files or add your book in reader. Download and read online ebook Fighting Back the Von Neumann Bottleneck with Small- and Large-Scale Vector Microprocessors write by Matheus Cavalcante. This book was released on 2023-08-24. Fighting Back the Von Neumann Bottleneck with Small- and Large-Scale Vector Microprocessors available in PDF, EPUB and Kindle. In his seminal Turing Award Lecture, Backus discussed the issues stemming from the word-at-a-time style of programming inherited from the von Neumann computer. More than forty years later, computer architects must be creative to amortize the von Neumann Bottleneck (VNB) associated with fetching and decoding instructions which only keep the datapath busy for a very short period of time. In particular, vector processors promise to be one of the most efficient architectures to tackle the VNB, by amortizing the energy overhead of instruction fetching and decoding over several chunks of data. This work explores vector processing as an option to build small and efficient processing elements for large-scale clusters of cores sharing access to tightly-coupled L1 memory
An Open-Source Research Platform for Heterogeneous Systems on Chip
An Open-Source Research Platform for Heterogeneous Systems on Chip - read free eBook in online reader or directly download on the web page. Select files or add your book in reader. Download and read online ebook An Open-Source Research Platform for Heterogeneous Systems on Chip write by Andreas Dominic Kurth. This book was released on 2022-10-05. An Open-Source Research Platform for Heterogeneous Systems on Chip available in PDF, EPUB and Kindle. Heterogeneous systems on chip (HeSoCs) combine general-purpose, feature-rich multi-core host processors with domain-specific programmable many-core accelerators (PMCAs) to unite versatility with energy efficiency and peak performance. By virtue of their heterogeneity, HeSoCs hold the promise of increasing performance and energy efficiency compared to homogeneous multiprocessors, because applications can be executed on hardware that is designed for them. However, this heterogeneity also increases system complexity substantially. This thesis presents the first research platform for HeSoCs where all components, from accelerator cores to application programming interface, are available under permissive open-source licenses. We begin by identifying the hardware and software components that are required in HeSoCs and by designing a representative hardware and software architecture. We then design, implement, and evaluate four critical HeSoC components that have not been discussed in research at the level required for an open-source implementation: First, we present a modular, topology-agnostic, high-performance on-chip communication platform, which adheres to a state-of-the-art industry-standard protocol. We show that the platform can be used to build high-bandwidth (e.g., 2.5 GHz and 1024 bit data width) end-to-end communication fabrics with high degrees of concurrency (e.g., up to 256 independent concurrent transactions). Second, we present a modular and efficient solution for implementing atomic memory operations in highly-scalable many-core processors, which demonstrates near-optimal linear throughput scaling for various synthetic and real-world workloads and requires only 0.5 kGE per core. Third, we present a hardware-software solution for shared virtual memory that avoids the majority of translation lookaside buffer misses with prefetching, supports parallel burst transfers without additional buffers, and can be scaled with the workload and number of parallel processors. Our work improves accelerator performance for memory-intensive kernels by up to 4×. Fourth, we present a software toolchain for mixed-data-model heterogeneous compilation and OpenMP offloading. Our work enables transparent memory sharing between a 64-bit host processor and a 32-bit accelerator at overheads below 0.7 % compared to 32-bit-only execution. Finally, we combine our contributions to a research platform for state-of-the-art HeSoCs and demonstrate its performance and flexibility.
