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IEEE STD 1800-2009
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IEEE STD 1800-2009: IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language
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IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language - Redline
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1800-2009 IEEE Standard for System Verilog-Unified Hardware Design, Specification, and Verification Language
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