Low Complexity, High Speed VLSI Architectures for Error Correction Decoders - read free eBook in online reader or directly download on the web page. Select files or add your book in reader. Download and read online ebook Low Complexity, High Speed VLSI Architectures for Error Correction Decoders write by Yanni Chen. This book was released on 2003. Low Complexity, High Speed VLSI Architectures for Error Correction Decoders available in PDF, EPUB and Kindle.
VLSI Architectures for Modern Error-Correcting Codes
VLSI Architectures for Modern Error-Correcting Codes - read free eBook in online reader or directly download on the web page. Select files or add your book in reader. Download and read online ebook VLSI Architectures for Modern Error-Correcting Codes write by Xinmiao Zhang. This book was released on 2017-12-19. VLSI Architectures for Modern Error-Correcting Codes available in PDF, EPUB and Kindle. Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI Architectures for Modern Error-Correcting Codes serves as a bridge connecting advancements in coding theory to practical hardware implementations. Instead of focusing on circuit-level design techniques, the book highlights integrated algorithmic and architectural transformations that lead to great improvements on throughput, silicon area requirement, and/or power consumption in the hardware implementation. The goal of this book is to provide a comprehensive and systematic review of available techniques and architectures, so that they can be easily followed by system and hardware designers to develop en/decoder implementations that meet error-correcting performance and cost requirements. This book can be also used as a reference for graduate-level courses on VLSI design and error-correcting coding. Particular emphases are placed on hard- and soft-decision Reed-Solomon (RS) and Bose-Chaudhuri-Hocquenghem (BCH) codes, and binary and non-binary low-density parity-check (LDPC) codes. These codes are among the best candidates for modern and emerging applications due to their good error-correcting performance and lower implementation complexity compared to other codes. To help explain the computations and en/decoder architectures, many examples and case studies are included. More importantly, discussions are provided on the advantages and drawbacks of different implementation approaches and architectures.
Low-Power VLSI Architectures for Error Control Coding and Wavelets
Low-Power VLSI Architectures for Error Control Coding and Wavelets - read free eBook in online reader or directly download on the web page. Select files or add your book in reader. Download and read online ebook Low-Power VLSI Architectures for Error Control Coding and Wavelets write by . This book was released on 2001. Low-Power VLSI Architectures for Error Control Coding and Wavelets available in PDF, EPUB and Kindle. This final report provides a brief summary of our research results supported by the above grant during the period from May 1,1998 to November 30, 2001. Our research has addressed design of high-speed, low-energy, low-area architectures for signal processing systems and error control coders. Contributions in the area of error control coding architectures include design of low-energy and low-complexity finite field arithmetic architectures and Reed-Solomon (RS) codecs. High- performance and low-power architectures for low-density parity-check (LDPC) codes have been developed.
Efficient Decoder Design for Error Correction Codes
Efficient Decoder Design for Error Correction Codes - read free eBook in online reader or directly download on the web page. Select files or add your book in reader. Download and read online ebook Efficient Decoder Design for Error Correction Codes write by Jinjin He. This book was released on 2010. Efficient Decoder Design for Error Correction Codes available in PDF, EPUB and Kindle. Error correction codes (ECCs) have been widely used in communication systems and storage devices. Nowadays, the rapid development of integrated circuit technologies makes feasible the implementation of powerful ECCs such as turbo code and low-density parity-check (LDPC) code. However, these high-performance codes require complex decoding algorithms, resulting in large hardware area and high power consumption. Furthermore, some of these decoders require an iterative decoding process, which leads to a long decoding latency. Therefore, low-complexity, low-power and high-speed very-large-scale integration (VLSI) architecture design for the ECC decoder is of great importance. This dissertation focuses on efficient VLSI implementation for the decoders of convolutional codes and two advanced coding schemes based on convolutional code: trellis-coded modulation (TCM) and convolutional turbo code (CTC). The first part of this dissertation is dedicated to low-complexity, low-power decoders design for a 4-dimensional, 8-ary phase-shift keying (4-D 8PSK) TCM system. We propose a low-complexity architecture for the transition-metric unit (TMU) to reduce the hardware area without performance loss. Then, a power-efficient scheme by applying T-algorithm on branch metrics (BMs) is proposed for the Viterbi decoder (VD) embedded in the 4-D 8PSK TCM decoder. Unlike the conventional T-algorithm, the proposed scheme does not affect the clock speed of the decoder. Finally, a hybrid T-algorithm is developed by applying T-algorithm on both BMs and path metrics (PMs), which reduces significantly more computations than the conventional T-algorithm applied on PMs. The VLSI design for VDs has been an active research area for decades. In the second part of the dissertation, we extend our research to a more general topic of VDs, where novel architectures are explored to efficiently reduce the power consumption, while still maintaining a high decoding speed and a low decoding latency. CTCs are constructed from parallel convolutional encoding of the same message in different sequences and have the error-correcting capability near the Shannon bound. Practical decoding schemes normally require an iterative decoding process employing the soft-in soft-out (SISO) decoder. The third part of this dissertation is focused on the SISO decoder design for double-binary (DB) CTCs. We propose a low-complexity, memory-reduced architecture by partitioning BMs into two independent portions: information metrics and parity metrics. Furthermore, high-speed recursion architectures for logarithm domain maximum a posteriori probability (log-MAP) algorithm are proposed to increase the decoding speed by algorithmic approximation and bit-level optimization.
High-speed VLSI Architectures for Error-correcting Codes and Cryptosystems
High-speed VLSI Architectures for Error-correcting Codes and Cryptosystems - read free eBook in online reader or directly download on the web page. Select files or add your book in reader. Download and read online ebook High-speed VLSI Architectures for Error-correcting Codes and Cryptosystems write by Xinmiao Zhang. This book was released on 2005. High-speed VLSI Architectures for Error-correcting Codes and Cryptosystems available in PDF, EPUB and Kindle.
