Power Efficient Analog-to-digital Converters Using Both Voltage and Time Domain Information - read free eBook in online reader or directly download on the web page. Select files or add your book in reader. Download and read online ebook Power Efficient Analog-to-digital Converters Using Both Voltage and Time Domain Information write by Taehwan Oh. This book was released on 2013. Power Efficient Analog-to-digital Converters Using Both Voltage and Time Domain Information available in PDF, EPUB and Kindle. As advanced wired and wireless communication systems attempt to achieve higher performance, the demand for high resolution and wide signal bandwidth in their associated ADCs is strongly increased. Recently, time-domain quantization has drawn attention from its scalability in deep submicron CMOS processes. Furthermore, there are several interesting aspects of time-domain quantizer by processing the signal in time rather than only in voltage domain especially for power efficiency. This research focuses on developing a new architecture for power efficient, high resolution ADCs using both voltage and time domain information. As a first approach, a new [delta sigma] ADC based on a noise-shaped two-step integrating quantizer which quantizes the signal in voltage and time domains is presented. Attaining an extra order of noise-shaping from the integrating quantizer, the proposed [delta sigma] ADC manifests a second-order noise-shaping with a first-order loop filter. Furthermore, this quantizer provides an 8b uantization in itself, drastically reducing the oversampling requirement. The proposed ADC also incorporates a new feedback DAC topology that alleviates the feedback DAC complexity of a two-step 8b quantizer. The measured results of the prototype ADC implemented in a 0.13[micro]m CMOS demonstrate peak SNDR of 70.7dB (11.5b ENOB) at 8.1mW power, with an 8x OSR at 80MHz sampling frequency. To further improve ADC performance, a Nyquist ADC based on a time-based pipelined TDC is also proposed as a second approach. In this work, a simple V-T conversion scheme with a cheap low gain amplifier in its first stage and a hybrid time-domain quantization stage based on simple charge pump and capacitive DAC in its backend stages, are also proposed to improve ADC linearity and power efficiency. Using voltage and time domain information, the proposed ADC architecture is beneficial for both resolution and power efficiency, with MSBs resolved in voltage domain and LSBs in time domain. The measured results of the prototype ADC implemented in a 0.13[micro]m CMOS demonstrate peak SNDR of 69.3dB (11.2b ENOB) at 6.38mW power and 70MHz sampling frequency. The FOM is 38.2fJ/conversion-step.
Time-interleaved Analog-to-Digital Converters
Time-interleaved Analog-to-Digital Converters - read free eBook in online reader or directly download on the web page. Select files or add your book in reader. Download and read online ebook Time-interleaved Analog-to-Digital Converters write by Simon Louwsma. This book was released on 2010-09-08. Time-interleaved Analog-to-Digital Converters available in PDF, EPUB and Kindle. Time-interleaved Analog-to-Digital Converters describes the research performed on low-power time-interleaved ADCs. A detailed theoretical analysis is made of the time-interleaved Track & Hold, since it must be capable of handling signals in the GHz range with little distortion, and minimal power consumption. Timing calibration is not attractive, therefore design techniques are presented which do not require timing calibration. The design of power efficient sub-ADCs is addressed with a theoretical analysis of a successive approximation converter and a pipeline converter. It turns out that the first can consume about 10 times less power than the latter, and this conclusion is supported by literature. Time-interleaved Analog-to-Digital Converters describes the design of a high performance time-interleaved ADC, with much attention for practical design aspects, aiming at both industry and research. Measurements show best-inclass performance with a sample-rate of 1.8 GS/s, 7.9 ENOBs and a power efficiency of 1 pJ/conversion-step.
Low-Power High-Resolution Analog to Digital Converters
Low-Power High-Resolution Analog to Digital Converters - read free eBook in online reader or directly download on the web page. Select files or add your book in reader. Download and read online ebook Low-Power High-Resolution Analog to Digital Converters write by Amir Zjajo. This book was released on 2010-10-29. Low-Power High-Resolution Analog to Digital Converters available in PDF, EPUB and Kindle. With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurements from the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.
Efficient Use of Time Information in Analog-to-digital Converters
Efficient Use of Time Information in Analog-to-digital Converters - read free eBook in online reader or directly download on the web page. Select files or add your book in reader. Download and read online ebook Efficient Use of Time Information in Analog-to-digital Converters write by Yue Hu. This book was released on 2014. Efficient Use of Time Information in Analog-to-digital Converters available in PDF, EPUB and Kindle. Time-domain data conversion has recently drawn increased research attention for its highly digital nature in favor of process technology scaling. Also, as the time information being carried by binary voltage, time-domain operation is much less sensitive to voltage noise compared to conventional voltage domain operation. However, for analog-to-digital converter (ADC) application, the challenge lies in the methodology of benefiting from time-domain operation while maintaining/improving the overall data conversion accuracy and power efficiency. This dissertation has a focus on the investigation of novel data conversion topologies based on classic voltage domain operation that is capable of generating time information, to improve ADC resolution, system stability and speed without power penalty. In the first approach, a novel continuous-time (CT) delta-sigma modulator (DSM) using a time-interleaved quantizer is proposed and implemented. Along with the doubled sample rate, the proposed architecture utilizes time information to perform correlated coupling between the two quantizer channels. A 120MS/s CT [delta sigma] ADC using proposed technique is implemented in 0.18 [micro]m CMOS process. The measurement results achieve second order noise coupling from the interleaved quantizer itself without extra phases. More importantly, excess loop delay of two full sample clocks is compensated by time-domain signal coupling; the resulted CT DSM is fully stabilized in 120MHz sampling rate and achieves 11 effective number of bits (ENOB). In the second approach, a new category of pulse-width-modulation (PWM) scheme is proposed and described: time symmetric PWM (TSPWM). An ADC structure is further proposed and implemented utilizing this novel voltage-to-time converter, followed by a first order noise-shaped switched-ring-oscillator (SRO) TDC quantizer. This ADC topology takes advantage of the TDC speed scaling for its digitized operation to boost the overall ADC resolution and signal bandwidth, while the voltage-to-time front-end is able to remain at a much lower speed than the TDC, thanks to the proposed technique. This is the first work that decouples the PWM modulation rate from TDC quantizing speed without distortion penalty. Built in 0.18 [micro]m, the implemented ADC is able to sample at a range from 20MHz to 40MHz, the generated pulse train is quantized by the following SRO TDC at a rate of 400MHz. The prototype chip shows a SFDR improvement over 24dB on the ADC output when TSPWM is used.
Design of Power-Efficient Highly Digital Analog-to-Digital Converters for Next-Generation Wireless Communication Systems
Design of Power-Efficient Highly Digital Analog-to-Digital Converters for Next-Generation Wireless Communication Systems - read free eBook in online reader or directly download on the web page. Select files or add your book in reader. Download and read online ebook Design of Power-Efficient Highly Digital Analog-to-Digital Converters for Next-Generation Wireless Communication Systems write by Xinpeng Xing. This book was released on 2017-10-04. Design of Power-Efficient Highly Digital Analog-to-Digital Converters for Next-Generation Wireless Communication Systems available in PDF, EPUB and Kindle. This book discusses both architecture- and circuit-level design aspects of voltage-controlled-oscillator (VCO)-based analog-to-digital converters (ADCs), especially focusing on mitigation of VCO nonlinearity and the improvement of power efficiency. It shows readers how to develop power-efficient complementary-metal-oxide-semiconductor (CMOS) ADCs for applications such as LTE, 802.11n, and VDSL2+. The material covered can also be applied to other specifications and technologies. Design of Power-Efficient Highly Digital Analog-to-Digital Converters for Next-Generation Wireless Communication Systems begins with a general introduction to the applications of an ADC in communications systems and the basic concepts of VCO-based ADCs. The text addresses a wide range of converter architectures including open- and closed-loop technologies. Special attention is paid to the replacement of power-hungry analog blocks with VCO-based circuits and to the mitigation of VCO nonline arity. Various MATLAB®/Simulink® models are provided for important circuit nonidealities, allowing designers and researchers to determine the required specifications for the different building blocks that form the systematic integrated-circuit design procedure. Five different VCO-based ADC design examples are presented, introducing innovations at both architecture and circuit levels. Of these designs, the best power efficiency of a high-bandwidth oversampling ADC is achieved in a 40 nm CMOS demonstration. This book is essential reading material for engineers and researchers working on low-power-analog and mixed-signal design and may be used by instructors teaching advanced courses on the subject. It provides a clear overview and comparison of VCO-based ADC architectures and gives the reader insight into the most important circuit imperfections.
