Reliability of high-k / metal gate field-effect transistors considering circuit operational constraints - read free eBook in online reader or directly download on the web page. Select files or add your book in reader. Download and read online ebook Reliability of high-k / metal gate field-effect transistors considering circuit operational constraints write by Steve Kupke. This book was released on 2016-06-06. Reliability of high-k / metal gate field-effect transistors considering circuit operational constraints available in PDF, EPUB and Kindle. After many decades, the scaling of silicon dioxide based field-effect transistors has reached insurmountable physical limits due unintentional high gate leakage currents for gate oxide thicknesses below 2 nm. The introduction of high-k metal gate stacks guaranteed the trend towards smaller transistor dimensions. The implementation of HfO2, as high-k dielectric, also lead to a substantial number of manufacturing and reliability challenges. The deterioration of the gate oxide properties under thermal and electric stress jeopardizes the circuit operation and hence needs to be comprehensively understood. As a starting point, 6T static random access memory cells were used to identify the different single device operating conditions. The strongest deterioration of the gate stack was found for nMOS devices under positive bias temperature instability (PBTI) stress, resulting in a severe threshold voltage shift and increased gate leakage current. A detailed investigation of physical origin and temperature and voltage dependency was done. The reliability issues were caused by the electron trapping into already existing HfO2 oxygen vacancies. The oxygen vacancies reside in different charge states depending on applied stress voltages. This in return also resulted in a strong threshold voltage and gate current relaxation after stress was cut off. The reliability assessment using constant voltage stress does not reflect realistic circuit operation which can result in a changed degradation behaviour. Therefore, the constant voltage stress measurement were extended by considering CMOS operational constraints, where it was found that the supply voltage frequently switches between the gate and drain terminal. The additional drain (off-state) bias lead to an increased Vt relaxation in comparison to zero bias voltage. The off-state influence strongly depended on the gate length and became significant for short channel devices. The influence of the off-state bias on the dielectric breakdown was studied and compared to the standard assessment methods. Different wear-out mechanisms for drain-only and alternating gate and drain stress were verified. Under drain-only stress, the dielectric breakdown was caused by hot carrier degradation. The lifetime was correlated with the device length and amount of subthreshold leakage. The gate oxide breakdown under alternating gate and o-state stress was caused by the continuous trapping and detrapping behaviour of high-k metal gate devices.
Formation of Ferroelectricity in Hafnium Oxide Based Thin Films
Formation of Ferroelectricity in Hafnium Oxide Based Thin Films - read free eBook in online reader or directly download on the web page. Select files or add your book in reader. Download and read online ebook Formation of Ferroelectricity in Hafnium Oxide Based Thin Films write by Tony Schenk. This book was released on 2017-03-15. Formation of Ferroelectricity in Hafnium Oxide Based Thin Films available in PDF, EPUB and Kindle. In 2011, Böscke et al. reported the unexpected discovery of ferroelectric properties in hafnia based thin films, which has since initiated many further studies and revitalized research on the topic of ferroelectric memories. In spite of many efforts, the unveiling of the fundamentals behind this surprising discovery has proven rather challenging. In this work, the originally claimed Pca21 phase is experimentally proven to be the root of the ferroelectric properties and the nature of this ferroelectricity is classified in the frame of existing concepts of ferroelectric materials. Parameters to stabilize this polar phase are examined from a theoretical and fabrication point of view. With these very basic questions addressed, the application relevant electric field cycling behavior is studied. The results of first-order reversal curves, impedance spectroscopy, scanning transmission electron microscopy and piezoresponse force microscopy significantly advance the understanding of structural mechanisms underlying wake-up, fatigue and the novel phenomenon of split-up/merging of transient current peaks. The impact of field cycling behavior on applications like ferroelectric memories is highlighted and routes to optimize it are derived. These findings help to pave the road for a successful commercialization of hafnia based ferroelectrics.
High-k Materials in Multi-Gate FET Devices
High-k Materials in Multi-Gate FET Devices - read free eBook in online reader or directly download on the web page. Select files or add your book in reader. Download and read online ebook High-k Materials in Multi-Gate FET Devices write by Shubham Tayal. This book was released on 2021-09-17. High-k Materials in Multi-Gate FET Devices available in PDF, EPUB and Kindle. High-k Materials in Multi-Gate FET Devices focuses on high-k materials for advanced FET devices. It discusses emerging challenges in the engineering and applications and considers issues with associated technologies. It covers the various way of utilizing high-k dielectrics in multi-gate FETs for enhancing their performance at the device as well as circuit level. Provides basic knowledge about FET devices Presents the motivation behind multi-gate FETs, including current and future trends in transistor technologies Discusses fabrication and characterization of high-k materials Contains a comprehensive analysis of the impact of high-k dielectrics utilized in the gate-oxide and the gate-sidewall spacers on the GIDL of emerging multi-gate FET architectures Offers detailed application of high-k materials for advanced FET devices Considers future research directions This book is of value to researchers in materials science, electronics engineering, semiconductor device modeling, IT, and related disciplines studying nanodevices such as FinFET and Tunnel FET and device-circuit codesign issues.
Low-Power Variation-Tolerant Design in Nanometer Silicon
Low-Power Variation-Tolerant Design in Nanometer Silicon - read free eBook in online reader or directly download on the web page. Select files or add your book in reader. Download and read online ebook Low-Power Variation-Tolerant Design in Nanometer Silicon write by Swarup Bhunia. This book was released on 2010-11-10. Low-Power Variation-Tolerant Design in Nanometer Silicon available in PDF, EPUB and Kindle. Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. We consider both logic and memory design aspects and cover modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. This book will discuss current industrial practices and emerging challenges at future technology nodes.
Mitigating Process Variability and Soft Errors at Circuit-Level for FinFETs
Mitigating Process Variability and Soft Errors at Circuit-Level for FinFETs - read free eBook in online reader or directly download on the web page. Select files or add your book in reader. Download and read online ebook Mitigating Process Variability and Soft Errors at Circuit-Level for FinFETs write by Alexandra Zimpeck. This book was released on 2021-03-10. Mitigating Process Variability and Soft Errors at Circuit-Level for FinFETs available in PDF, EPUB and Kindle. This book evaluates the influence of process variations (e.g. work-function fluctuations) and radiation-induced soft errors in a set of logic cells using FinFET technology, considering the 7nm technological node as a case study. Moreover, for accurate soft error estimation, the authors adopt a radiation event generator tool (MUSCA SEP3), which deals both with layout features and electrical properties of devices. The authors also explore four circuit-level techniques (e.g. transistor reordering, decoupling cells, Schmitt Trigger, and sleep transistor) as alternatives to attenuate the unwanted effects on FinFET logic cells. This book also evaluates the mitigation tendency when different levels of process variation, transistor sizing, and radiation particle characteristics are applied in the design. An overall comparison of all methods addressed by this work is provided allowing to trace a trade-off between the reliability gains and the design penalties of each approach regarding the area, performance, power consumption, single event transient (SET) pulse width, and SET cross-section.
